A silicon-carbide semiconductor device has been used as a high-withstanding voltage, low-loss semiconductor device capable of switching at a high speed. Particularly, a trench-gate silicon-carbide semiconductor device has a higher channel density per unit area, and thus it has a greater current amount, as compared to a general planar silicon-carbide semiconductor device. A reduction in the ON-resistance is expected in such a trench-gate silicon-carbide semiconductor device.
In the trench-gate silicon-carbide semiconductor device in general, an epitaxial layer of a low-defect-density n-type semiconductor is formed on an n-type semiconductor substrate, and a p-type semiconductor layer is formed in addition. An n-type high-concentration layer (an n+ layer) connected to a source electrode and a p-type high-concentration layer (a p+ layer) connected to the p-type semiconductor layer described above are formed on the surface. A trench is formed so as to penetrate through the p-type semiconductor layer.
In the trench-gate silicon-carbide semiconductor device, a gate insulating film and a gate-electrode material are embedded within the trench to form a gate electrode. Generally, the trench is formed in an elongated shape. Therefore, the high density of the gate electrode can be obtained, as compared to the planar silicon-carbide semiconductor device where a flat gate electrode is formed on the surface of the semiconductor device. Such a high density of the gate electrode can increase the channel density per unit area, and thus a reduction in ON-resistance can be achieved. However, the trench is formed deeply, so that the distance between a drain electrode on the back side of the silicon-carbide semiconductor device and the gate electrode within the trench may be set to be small. Such a short distance may cause high electric field intensity between them. In such a case, a dielectric breakdown may occur. Therefore, it is difficult to simultaneously achieve high efficiency and a high withstanding voltage by reducing the ON-resistance.
A structure for improving the withstanding voltage for this problem is proposed in a technique in which a p-type well region is formed at a location apart from the trench so as to have a depth that is equal to or greater than that of the trench (Patent Literature 1). A depletion layer extends from a junction between this deep p-type well region and an n-type drift layer just below the p-type well region, so that the bottom of the trench is protected. This can reduce the electric field intensity between the gate insulating film and the drain electrode on the back side of the silicon-carbide semiconductor device, and thus the withstanding voltage can be increased.